It would useful to be able to carry out GPIO fast state changes and simultaneous multiple bit changes.
This is achieved on some other Linux platforms by setting or clearing bits in registers mapped at memory addresses. The following is an example for a different SoC and openWRT. I don’t know if this is a good example. But I do know that similar performance is obtainable with the Raspberry Pi SoC
Yes that is understandable. But the performance of file based IO is very poor (as pointed out to me again by a customer today). Also I think the current latency through the IPC api also has a significant impact on IO performance.
Maybe the answer is for Sierra to supply a linkable library that hides the hardware implementation but has little impact on IO performance ?
I notice that there is an open issue in the release notes
Only one service is able to access a GPIO pin at a time
Perhaps when that issue is addressed the speed can be addressed as well?
Originally someone asked me to implement a demo using a 1-wire device (bit bash) - not a good use case as the timing would be too tricky in Linux and so I didn’t post this on the forum.
Since then a couple of customers + @davidc have brought up the issue of long latency / slow IO for various reasons including parallel bus emulation via GPIO. I think in these cases the actual timing is not critical but bandwidth / latency is an issue.