SPI transfer: actual transfered bytes are more than expected



I’m using WP7702 SPI to transfer data from an external microcontroller to the WP7702.
I’m using the spisvc Linux driver provided with Legato in order to perform an SPI transfer with an userspace app.
The problem is that if I want to transfer 22 bytes, on the bus I get a 24 bytes transfer.

I’m using an oscilloscope capable of SPI analysis and it detects a 24 bytes transfer, and I’m able to see 24 clock cycles on SCK. So the cause of the problem is the WP/Linux emitting 24 clock pulses instead of 22.

The spisvc.c is configured this way:
struct spi_master *m = NULL;
struct spi_board_info board = {
.modalias = “spidev”,
.max_speed_hz = 15058800,
.mode = SPI_MODE_1, // SPI_MODE_3,
.platform_data = NULL,
.bus_num = 0,
.chip_select = 0,
.irq = 0,

The SPI transfer is performed this way:
struct spi_ioc_transfer xfer[] = { { .rx_buf = (unsigned long)pBuf, .len = 22 } };
status = ioctl( fd, SPI_IOC_MESSAGE(1), xfer);
if (status < 0) {
log(“spi read error code: %d”, status);
return -1;
logd(“spi: read #%d bytes (header)”, xfer[0].len);

Does anyone know why this happens?

A few tests leaded to these hints:

transfer shorter than 20 bytes result in the right number of bytes transfered on the bus;
changing the clock speed is not influent: I tested at 1MHz too (instead of 15 MHz) but the result is the same;



We can suggest you to reduce the clock frequency i.e “.max_speed_hz” in dts file.
If 15058800 is related to 24 clock cycles.Can you please check with reducing to 15000000(< 15058800)?
this might reduce number of clock pulses.


I think this has a relationship with the spi modes, precisely with clock polarity and clock phase, so try to change the modes, the best is to use mode 0 because is not inverted clock.


I want to know please, if your issue is solved or no ? if no, have you tried to apply our suggestions?