# Swi-mdm9x28 Device tree

**URL:** <https://forum.legato.io/t/swi-mdm9x28-device-tree/3123>\
**Category:** Legato Linux distribution (Yocto project)\
**Created:** [March 5, 2018, 3:35pm UTC](https://forum.legato.io/t/swi-mdm9x28-device-tree/3123 "2018-03-05T15:35:21Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![Souhail](https://avatars.discourse-cdn.com/v4/letter/s/a698b9/32.png) [@Souhail](https://forum.legato.io/u/Souhail)\
**Post date:** [March 5, 2018, 3:35pm UTC](https://forum.legato.io/t/swi-mdm9x28-device-tree/3123/1 "2018-03-05T15:35:21Z")

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Hi,

Does any one have an idea about the SPI interface on which device tree file is defined for the WP7607 yocto distibution, I need to add an SPI driver and I want to bound the “of\_device\_id” table with the spidev1.0 that is used for the spidev API.

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<div class="post-metadata">

**Author:** ![CoRfr](https://sea1.discourse-cdn.com/flex019/user_avatar/forum.legato.io/corfr/32/69_2.png) [@CoRfr](https://forum.legato.io/u/CoRfr)\
**Post date:** [March 5, 2018, 7:05pm UTC](https://forum.legato.io/t/swi-mdm9x28-device-tree/3123/2 "2018-03-05T19:05:32Z")

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Hi @Souhail,

I think this would be `arch/arm/boot/dts/qcom/mdm9607-wp76xx.dtsi`

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<div class="post-metadata">

**Author:** ![Souhail](https://avatars.discourse-cdn.com/v4/letter/s/a698b9/32.png) [@Souhail](https://forum.legato.io/u/Souhail)\
**Post date:** [March 7, 2018, 3:14pm UTC](https://forum.legato.io/t/swi-mdm9x28-device-tree/3123/3 "2018-03-07T15:14:22Z")

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Thank you for your help, by refering to this file and mdm9607-pinctrl.dtsi I could not found how the spi1 interface is bounded with the pins 51, 52, 53, 55 from the chip. Do you have any idea please ?

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<div class="post-metadata">

**Author:** ![Manukumar](https://avatars.discourse-cdn.com/v4/letter/m/eada6e/32.png) [@Manukumar](https://forum.legato.io/u/Manukumar)\
**Post date:** [April 17, 2018, 12:28pm UTC](https://forum.legato.io/t/swi-mdm9x28-device-tree/3123/4 "2018-04-17T12:28:23Z")

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Hi,

SPI can be bound with the pins to which it has been allocated we can also use GPIO lines. Also If we look at the dtsi file we can see how the pins are organized such as which pin is used MOSI,MISO,Clock and IRQ lines. Below is SPI configuration we see in mdm9607-pinctrl.dtsi where gpio0 - gpio7 are used.

spi1\_sleep: spi1\_sleep {  
/\* suspended state _/  
mux {  
/_ MOSI, MISO, CLK \*/  
pins = “gpio4”, “gpio5”, “gpio7”;  
function = “gpio”;  
};

```
                            config {
                                    pins = "gpio4", "gpio5", "gpio7";
                                    drive-strength = <2>; /* 2 MA */
                                    bias-pull-down; /* PULL Down */
                            };
                    };

```

spi\_0: spi\_hub: spi@f9926000 {  
compatible = “qlspi,qlspi\_eoss3”;  
reg = \<1\>;  
interrupt-parent = \<&msmgpio\>;  
interrupts = \<94 0\>;  
/\* spi-max-frequency = \<18000000\>; _/  
spi-max-frequency = \<6000000\>;  
qlspi,irq-gpio = \<&msmgpio 59 0x00\>;  
qlspi,cs-gpio = \<&msmgpio 21 0x00\>;  
qlspi,mosi-gpio = \<&msmgpio 52 0x00\>;  
qlspi,miso-gpio = \<&msmgpio 53 0x00\>;  
qlspi,clk-gpio = \<&msmgpio 58 0x00\>;  
/_ qlspi,sw\_intr\_1\_gpio = \<&msmgpio 94 0x00\>; _/  
/_ SPI device on the slave device which it has to enumerate in spi\_0 dev node.  
spidev0@1 {  
compatible = “sierra,spidev”;  
spi-max-frequency = \<50000000\>;  
reg = \<0\>;  
};  
};

In the above example 52 is for mosi,53 is for miso,58 is clock and 21 is chip select which is defined as part of SOC.