# Controlling DCD, DTR, DSR lines by legato application **URL:** \ **Category:** Uncategorized\ **Created:** [December 13, 2018, 1:12pm UTC](https://forum.legato.io/t/controlling-dcd-dtr-dsr-lines-by-legato-application/3944 "2018-12-13T13:12:40Z")\ **Posts on this page:** 1\ **Showing post:** 11
**Author:** ![jyijyi](https://sea1.discourse-cdn.com/flex019/user_avatar/forum.legato.io/jyijyi/32/822_2.png) [@jyijyi](https://forum.legato.io/u/jyijyi)\ **Post date:** [January 9, 2019, 4:45am UTC](https://forum.legato.io/t/controlling-dcd-dtr-dsr-lines-by-legato-application/3944/11 "2019-01-09T04:45:58Z")
I don’t see there is such implementation on the coming release on WP76. However, I check the code (yocto/kernel/driver/gpio/gpiolib.c) of yocto of WP8548. I guess it is not difficult to implement. In WP76 yocto source code (yocto/kernel/driver/gpio/gpiolib-sysfs.c) , you can add some new GPIO in ext\_gpio\_map ext\_gpio\_wp: {“101”,xx,FUNCTION\_EMBEDDED\_HOST}, {“102”,xx,FUNCTION\_EMBEDDED\_HOST}, {“103”,xx,FUNCTION\_EMBEDDED\_HOST}, And map those xx number to the MDM CHIP UART DCD/DTR/DSR. After that you should be able to control in console like: echo 101 \> /sys/class/gpio/export echo out \> /sys/class/gpio/gpio101/direction echo 1 \> /sys/class/gpio/gpio101/value echo 102 \> /sys/class/gpio/export echo out \> /sys/class/gpio/gpio102/direction echo 1 \> /sys/class/gpio/gpio102/value echo 103 \> /sys/class/gpio/export echo out \> /sys/class/gpio/gpio103/direction echo 1 \> /sys/class/gpio/gpio103/value Currently I don’t have the information of xx of MDM CHIP UART number. And there might be potential issue that the 8-wire UART may also control those pins. I think you need to contact distributor of your region for the xx information or ask them for this new feature development in coming release. --- _[View the full topic](https://forum.legato.io/t/controlling-dcd-dtr-dsr-lines-by-legato-application/3944)._