I want to use macro,if that particular macro is enabled then only some files need be compile or else other files need to be compile.
How to include macro and how to make based on that macro files compilation?
The procedure for using the macro is as follows:
Create the Makefile.
Add below contents in the Makefile:
ifdef TEST_MACRO
all:
gcc -o a.out test.c
else
all:
gcc -o a.out test1.c
endif
Now create test.c file and test1.c file and put some significant print messages.
export TEST_MACRO=1 in the linux terminal.
Run Makefile with this command: make all
Run executable file a.out with ./a.out on the linux terminal.
Print message will be seen from test.c file.
File can be include or exclude for compiling via “#include<filename.h>”.
to control this via macro we can use #if,#ifndef, #endif, #elif with the flags.
Example:
#ifndef HEADER_FILE_NAME_H_
#include<file1.h>
#endif
#include<file2.h>
“condition_rule” needs to be included in Makefile
the rule can be -d option in makefile